Junior Processor Verification Engineer RISCV Contractor (San Francisco) Job at RISC-V, San Francisco, CA

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  • RISC-V
  • San Francisco, CA

Job Description

Job Description

RISC-V International is looking for a Junior level Verification Engineer to work as a part of the technical team focused specifically on certification program test development.

Time will be billed hourly as worked with a maximum of 40 hours / week. The expected salary range will be $8,000 to $10,000 per month based on experience.

Key responsibilities include:

  • Work as a member of the RISC-V International Technical Team and with the RISC-V CSC community to build and deliver certification tests and test plans
  • Attend RISC-V Certification Steering Committee (CSC) and work group meetings; collaborate with certification working groups members to support test case and test plan development and maintenance
  • Use simulation environments for Sail, Spike, QEMU, and others as-needed, to meet the CSC requirements for test evaluation and development
  • Execute within a tools-based, repeatable process for evaluating test case coverage using SystemVerilog-based coverage tools to measure certification tests
  • Collaborate with RISC-V open source test suite communities to improve test coverage through test suite development and maintenance work
  • Provide documentation creation and review of test setup, execution of selected test suites

Qualifications:
Qualifications

The following qualifications are required for consideration:

  • BS/BA degree in EE or ECE
  • 2-3 years developing processor verification tests
  • Mastery of UNIX/Linux-based scripting tools and languages make, bash, perl, Python, etc.
  • Experience with coverage-driven, verification testing
  • Experience with instruction set simulators (ISS)
  • Experience using SystemVerilog
  • Experience writing and configuring verification tests in a variety of environments including silicon, simulators and FPGA environments
  • Experience with GitHub, including CI/regression test automation

The following skills are preferred:

  • Masters or PhD in EE or ECE
  • RISC-V ISA and assembly language experience
  • Experience with QEMU, Spike, or Sail simulators.
  • Open Source software and hardware community experience

Additional Information

All your information will be kept confidential according to EEO guidelines.

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Job Tags

Hourly pay, Full time, For contractors,

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